The field of this invention relates to a radio frequency transmitter architecture, an integrated circuit device, a wireless communication unit and a method therefor. The invention is applicable to, but not limited to, a method of generating a radio frequency signal for transmission over a radio frequency (RF) interface.
Advances in the deep sub-micron CMOS (Complimentary Metal-Oxide Semiconductor) process have lead to digital circuits becoming smaller and more power efficient. However, it is known that analogue circuits do not scale particularly well with the deep sub-micron CMOS process. It is therefore desirable for devices, such as radio frequency (RF) transmitters, to remove as many analogue components or circuits as possible, for example with the assistance of digital signal processing algorithms, in order to be able to benefit from more use of deep sub-micron CMOS processes.
Furthermore, a large number of conventional RF transmitters use linear power amplifiers (PAs). Accordingly, the power efficiency of such conventional RF transmitters is usually very low, due to the low efficiency of the linear PAs used therein. Switch-mode PAs have very high efficiency in comparison, which make such switch-mode PAs an attractive alternative to conventional linear PAs within RF transmitters.
Thus, an RF transmitter that is able to utilize switch-mode PAs through the assistance of digital processing algorithms in order to reduce a PA's size and improve a PA's power efficiency is highly desirable. However, switch-mode PAs normally exhibit a highly non-linear input-output relationship. Furthermore, in order to meet stringent co-existence requirements of various wireless standards, noise shaping techniques are often required.
Digital polar transmitters are a type of known transmitter design that utilizes switch-mode PAs, whilst also taking advantage of CMOS process technology. Accordingly, such digital polar transmitters are able to achieve high power efficiency, whilst requiring only a small silicon area. However, a problem with these known transmitter designs is that, due to the inherent bandwidth expansion characteristics of the AM (amplitude modulation) and PM (phase modulation) signals in a polar architecture, they are only suitable for narrowband modulated signals.
Hybrid polar transmitter designs take advantage of two dimensional (in-phase/quadrature) modulation to enable wideband phase modulation to achieved. However, a problem with such hybrid polar transmitters is that they suffer from both amplitude and phase quantization noise, thus requiring significant noise shaping.
In-phase/Quadrature (IQ) RF digital-to-analogue converter (DAC) based transmitters are also known. I/Q RF DACs combine the functionalities of a DAC and a mixer, with the output of the I/Q RF DAC being combined in the analogue (RF) domain. However, such transmitter designs require a linear PA, and direct I/Q RF digital-to-analogue conversion is less power efficient than a digital polar transmitter design.
Another known (predominantly narrowband) RF transmitter design utilizes adaptive pre-distortion using a delta-sigma modulator for automatic inversion of power amplifier non-linearity. Such a design is relatively simple and allows for a use of low-precision DACs. However, this design still comprises a generally conventional architecture, and so PA efficiency is low.
It is anticipated that digitally-assisted/digitally-intensive RF transmitters will become increasingly desirable. However, digital algorithms are limited by the availability of circuit speed; therefore finding simple and effective digital algorithms is crucial from an implementation perspective. In published literature currently available there are sometimes discussions on digital algorithms that operate at very high clock frequencies, such as four times the carrier frequency. However, such clock frequencies are, in a practical CMOS and/or subscriber communication unit sense, not implementable.
Thus, a need exists for an improved RF transmitter, and method of operation therefor.